Patents by Inventor Roy D. Darling
Roy D. Darling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7536559Abstract: Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.Type: GrantFiled: May 5, 2005Date of Patent: May 19, 2009Assignee: Xilinx, Inc.Inventors: Jesse H. Jenkins, IV, Frank C. Wirtz, II, Roy D. Darling, Thomas J. Davies, Jr., Eric E. Edwards
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Patent number: 7180776Abstract: On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.Type: GrantFiled: February 1, 2005Date of Patent: February 20, 2007Assignee: Xilinx, Inc.Inventors: Wayne Edward Wennekamp, Eric E. Edwards, Roy D. Darling
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Patent number: 7127552Abstract: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.Type: GrantFiled: November 1, 2005Date of Patent: October 24, 2006Assignee: Xilinx, Inc.Inventors: Schuyler E. Shimanek, Roy D. Darling
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Patent number: 6981091Abstract: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.Type: GrantFiled: October 25, 2001Date of Patent: December 27, 2005Assignee: Xilinx,Inc.Inventors: Schuyler E. Shimanek, Roy D. Darling
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Patent number: 6873177Abstract: On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.Type: GrantFiled: August 12, 2003Date of Patent: March 29, 2005Assignee: Xilinx, Inc.Inventors: Wayne Edward Wennekamp, Eric E. Edwards, Roy D. Darling
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Patent number: 6714041Abstract: A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.Type: GrantFiled: August 30, 2002Date of Patent: March 30, 2004Assignee: Xilinx, Inc.Inventors: Roy D. Darling, Schuyler E. Shimanek, Thomas J. Davies, Jr.
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Publication number: 20030084230Abstract: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.Type: ApplicationFiled: October 25, 2001Publication date: May 1, 2003Applicant: Xilinx, Inc.Inventors: Schuyler E. Shimanek, Roy D. Darling
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Patent number: 5336951Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.Type: GrantFiled: August 13, 1993Date of Patent: August 9, 1994Assignee: Lattice Semiconductor CorporationInventors: Gregg R. Josephson, Ju Shen, Roy D. Darling, Chan-Chi J. Cheng
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Patent number: 5237218Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.Type: GrantFiled: May 3, 1991Date of Patent: August 17, 1993Assignee: Lattice Semiconductor CorporationInventors: Gregg R. Josephson, Ju Shen, Roy D. Darling, Chan-Chi J. Cheng
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Patent number: 4896296Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed.Type: GrantFiled: December 23, 1988Date of Patent: January 23, 1990Assignee: Lattice Semiconductor CorporationInventors: John E. Turner, David L. Rutledge, Roy D. Darling
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Patent number: 4879688Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed.Type: GrantFiled: May 13, 1986Date of Patent: November 7, 1989Assignee: Lattice Semiconductor CorporationInventors: John E. Turner, David L. Rutledge, Roy D. Darling
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Patent number: 4855954Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed.Type: GrantFiled: October 25, 1988Date of Patent: August 8, 1989Assignee: Lattice Semiconductor CorporationInventors: John E. Turner, David L. Rutledge, Roy D. Darling