Abstract: A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.

Abstract: Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.

Abstract: A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, connected in daisy chain configuration, process incoming information, and a decision is made whether each function entity will generate a blocking control or a pass-through control. The error messages are aggregated across the function entities in a single clock cycle with the help of an error controller. The functions can be from IEEE 1394 interface, graphics display controller, sound card, PCIe switch, or PCIe to PCI bridge connection. Each function preferably has a different configuration and security level setting for error reporting and messaging.

Abstract: Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.

Abstract: Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.

Abstract: A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.

Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.

Abstract: Methods and systems are provided for receiving and assembling serial data into parallel arrangements referred to as data slices. A plurality of data slices define a data line. Data slices common to a data line are written across like addresses of memory logically partitioned as memory slots. Respective memory slots are selected for data write operations in a successively advancing manner. As a result, a just-written data slice is immediately available for reading on the next clock cycle. Also, respective data slices can be simultaneously written to and read from the same or different memory slots on a particular clock cycle. Fast serial data communication between peripheral devices and other computer-related entities is performed accordingly.

Abstract: Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.