Patents by Inventor Roy David Wojciechowski

Roy David Wojciechowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11258630
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Roy David Wojciechowski
  • Publication number: 20210091972
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventor: Roy David WOJCIECHOWSKI
  • Patent number: 10892911
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Roy David Wojciechowski
  • Publication number: 20200076643
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Application
    Filed: May 22, 2019
    Publication date: March 5, 2020
    Inventor: Roy David WOJCIECHOWSKI
  • Patent number: 7818468
    Abstract: In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module including a first sub-level module, a second sub-level module operably coupleable to the first sub-level module, and a third sub-level module operably coupleable to the second module; and a second-level module operably coupleable to the first-level module is disclosed.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: October 19, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Elizabeth Anne Richard, Sumit Rupri Das, Paul Timothy Howard, Scott Adam Morrison, Pradipkuma A. Thaker, Roy David Wojciechowski
  • Publication number: 20090327527
    Abstract: In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module including a first sub-level module, a second sub-level module operably coupleable to the first sub-level module, and a third sub-level module operably coupleable to the second module; and a second-level module operably coupleable to the first-level module is disclosed.
    Type: Application
    Filed: June 29, 2008
    Publication date: December 31, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Elizabeth Anne Richard, Sumit Rupri Das, Paul Timothy Howard, Scott Adam Morrison, Pradipkuma A. Thaker, Roy David Wojciechowski