Patents by Inventor Roy Dittler
Roy Dittler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791228Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.Type: GrantFiled: April 10, 2019Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Kristof Darmawikarta, Roy Dittler, Jeremy Ecton, Darko Grujicic
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Patent number: 11501967Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.Type: GrantFiled: February 6, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Suddhasattwa Nad, Roy Dittler, Darko Grujicic, Marcel Wall, Rahul Manepalli
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Patent number: 11291122Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 22, 2017Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
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Publication number: 20220093535Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Applicant: Intel CorporationInventors: Benjamin Duong, Roy Dittler, Darko Grujicic, Chandrasekharan Nair, Rengarajan Shanmugam
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Publication number: 20220010452Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: Chandrasekharan NAIR, Darko GRUJICIC, Rengarajan SHANMUGAM, Srinivasan RAMAN, Roy DITTLER, Daniel SOWA, Robert BARESEL, II, Marcel WALL, Rahul MANEPALLI
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Publication number: 20210090946Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Darko GRUJICIC, Matthew ANDERSON, Adrian BAYRAKTAROGLU, Roy DITTLER, Benjamin DUONG, Tarek A. IBRAHIM, Rahul N. MANEPALLI, Suddhasattwa NAD, Rengarajan SHANMUGAM, Marcel WALL
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Publication number: 20200328131Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.Type: ApplicationFiled: April 10, 2019Publication date: October 15, 2020Inventors: Brandon C. MARIN, Kristof DARMAWIKARTA, Roy DITTLER, Jeremy ECTON, Darko GRUJICIC
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Patent number: 10798817Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: GrantFiled: December 11, 2015Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Aleksandar Aleksov, Javier Soto Gonzalez, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne
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Publication number: 20200251332Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: Suddhasattwa NAD, Roy DITTLER, Darko GRUJICIC, Marcel WALL, Rahul MANEPALLI
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Publication number: 20200245472Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2017Publication date: July 30, 2020Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
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Publication number: 20180376585Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: ApplicationFiled: December 11, 2015Publication date: December 27, 2018Inventors: Aleksandar Aleksov, Javier Soto Gonzalea, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne