Patents by Inventor Roy E. Swart

Roy E. Swart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10627427
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Roy E. Swart, Paul B. Fischer, Charlotte C. Kwong
  • Patent number: 10120020
    Abstract: Probe head assemblies and probe systems for testing integrated circuit devices are disclosed herein. In one embodiment, the probe head assemblies include a contacting structure and a space transformer assembly. In another embodiment, the probe head assemblies include a contacting structure, a suspension system, a flex cable interface, and a space transformer including a space transformer body and a flex cable assembly. In another embodiment, the probe head assemblies include a contacting structure, a space transformer, and a planarization layer. In another embodiment, the probe head assemblies include a contacting structure, a space transformer, a suspension system, a platen, a printed circuit board, a first plurality of signal conductors configured to convey a first plurality of signals external to the space transformer, and a second plurality of signal conductors configured to convey a second plurality of signals via the space transformer. The probe systems include the probe head assemblies.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 6, 2018
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Jay Salmon, Roy E. Swart, Brandon Liew
  • Publication number: 20180045760
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventors: Roy E. SWART, Paul B. FISCHER, Charlotte C. KWONG
  • Patent number: 9835648
    Abstract: Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Kimin Jun, Ting Zhong, Roy E. Swart, Paul B. Fischer
  • Publication number: 20170330677
    Abstract: Space transformers, planarization layers for space transformers, methods of fabricating space transformers, and methods of planarizing space transformers are disclosed herein. In one embodiment, the space transformers include a space transformer assembly including a first rigid space transformer layer, a second rigid space transformer layer, and an attachment layer that extends between the first rigid space transformer layer and the second rigid space transformer layer. In another embodiment, the space transformers include a space transformer body and a flex cable assembly. The planarization layer includes an interposer, a resilient dielectric layer, a planarized rigid dielectric layer, a plurality of holes, and an electrically conductive paste extending within the plurality of holes. In one embodiment, the methods include methods of fabricating the space transformer assembly. In another embodiment, the methods include methods of planarizing a space transformer.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Jay Salmon, Roy E. Swart, Brandon Liew
  • Patent number: 9391447
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin
  • Patent number: 9360502
    Abstract: Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The method also includes positioning an interface of the probe and the device in a liquid medium. The method also includes transmitting a current from the probe through the interface while the interface is in the liquid medium. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: June 7, 2016
    Assignee: INTEL CORPORATION
    Inventors: Warren S. Crippen, Brett Grossman, Roy E. Swart, Pooya Tadayon
  • Patent number: 9279830
    Abstract: The formation of test probe structures is described. One test probe structure includes a tip portion and a handle portion spaced a distance away from the tip portion. The test probe structure also includes a body bend portion positioned between the tip portion and the handle portion, and an intermediate portion positioned between the body bend portion and the handle portion. The body bend portion may include a curved shape extending from the intermediate portion to the tip portion. The tip portion may be formed to be offset from a longitudinal axis defined by the intermediate portion. The test probe structure defines a length and includes a cross-sectional area that is different at a plurality of positions along the length. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Roy E. Swart, Warren S. Crippen, Charlotte C. Kwong, David Shia
  • Publication number: 20150008950
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: January 8, 2015
    Inventors: Roy E. Swart, Paul B. Fischer, Charlotte C. Kwong
  • Publication number: 20140239995
    Abstract: The formation of test probe structures is described. One test probe structure includes a tip portion and a handle portion spaced a distance away from the tip portion. The test probe structure also includes a body bend portion positioned between the tip portion and the handle portion, and an intermediate portion positioned between the body bend portion and the handle portion. The body bend portion may include a curved shape extending from the intermediate portion to the tip portion. The tip portion may be formed to be offset from a longitudinal axis defined by the intermediate portion. The test probe structure defines a length and includes a cross-sectional area that is different at a plurality of positions along the length. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: August 28, 2014
    Inventors: Roy E. Swart, Warren S. Crippen, Charlotte C. Kwong, David Shia
  • Publication number: 20140210499
    Abstract: Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The method also includes positioning an interface of the probe and the device in a liquid medium. The method also includes transmitting a current from the probe through the interface while the interface is in the liquid medium. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 31, 2014
    Inventors: Warren S. Crippen, Brett Grossman, Roy E. Swart, Pooya Tadayon
  • Publication number: 20140029150
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Application
    Filed: March 6, 2012
    Publication date: January 30, 2014
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin
  • Patent number: 8513966
    Abstract: Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Qing Ma, Roy E. Swart, Paul B. Fischer, Johanna M. Swan
  • Publication number: 20130000117
    Abstract: Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Rajashree Baskaran, Kimin Jun, Ting Zhong, Roy E. Swart, Paul B. Fischer
  • Publication number: 20120038379
    Abstract: Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Inventors: Qing Ma, Roy E. Swart, Paul B. Fischer, Johanna M. Swan