Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Abstract: A circuit determines when a given operation has been performed and starts a counter. If a second operation, particularly an operation complementary to the first operation, is initiated before the counter reaches a predetermined value the second operation is held or delayed until the time is elapsed, after which time the second operation completes.

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace is routed from the source terminal of the net to a balanced junction wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads. The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches.

Abstract: A memory expansion board capable of holding up to 16 Mbytes of memory devices, using primarily 1 Mbit chips, in 2 Mbyte module increments, on a single IBM PC/AT compatible size board. The circuit board is so designed that when the memory expansion board is populated by modules and placed in a computer system it does not interfere with any of the other expansion slots within the computer system, all of the expansion slots being normally spaced apart. The memory expansion board also includes a means of protecting the memory expansion board and modules from damage due to misalignment when inserting the board and/or modules. When certain of the modules are inserted rotated 180 degrees the circuit board cannot be properly installed in the system board because of physical interference. Lastly, the memory expansion board includes a means for providing reduced length addressing memory lines to memory devices appearing on opposite sides of a circuit board.

Abstract: A method and apparatus for controlling two or more video display devices using a single display controller, where the display devices generally require different control data. Basic display control parameters are stored in a memory and, when the controller is to be switched from one display to another, the parameters are read from the memory into a substitution device. The substitution device receives modification control signals which depend on the newly selected display device and modifies the display control parameters before re-programming the display controller. The display controller then contains the parameters as appropriately modified for the currently controlled display device. The operator can switch from one monitor to another by generating an appropriate control signal, whereupon the substitution device again reads the control parameters from the memory, modifies them according to the newly selected display device, and re-programs the display controller using the modified parameters.

Abstract: Apparatus for maintenancing the brake drum carried by the spindle of a wheel axle assembly. The apparatus reduces both the time required to maintenance a brake drum and the likelihood that bearings and bearing seals in the brake drum will be damaged when the drum is removed from its spindle.