Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

Abstract: A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a look-up table comprising a set of entries, each entry having associated with it a domain and an approximation function for approximating F on the associated domain. The truncator unit is arranged to truncate or round a first value X1 to generate a second value X2. The selector unit is arranged to select an entry of the lookup-table according to the second value X2, thus selecting the approximation function that is associated with the selected entry. The evaluator unit is arranged to determine the function value of the selected approximation function at the first value X1.

Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.

Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

Abstract: A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a look-up table comprising a set of entries, each entry having associated with it a domain and an approximation function for approximating F on the associated domain. The truncator unit is arranged to truncate or round a first value X1 to generate a second value X2. The selector unit is arranged to select an entry of the lookup-table according to the second value X2, thus selecting the approximation function that is associated with the selected entry. The evaluator unit is arranged to determine the function value of the selected approximation function at the first value X1.

Abstract: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Abstract: A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second inputs and a carry-in bit. An output of the first adder is coupled to a first input of the third adder, and an output of the second adder is coupled to a second input of the third adder. The arithmetic circuitry is able to calculate an arithmetic operation on a set of four inputs. The arithmetic operation is fully determined by control bits and may be: an average of two values (with or without rounding by 1), an average of four values (with or without rounding by 1 or 2), or a sum of four values.

Abstract: An instruction packet having an extended machine language instruction may include at least a machine language instruction having encoded bits of an operation and a control word including bits of one or more extension fields. The structure and meaning of the extension fields may depend upon the extended machine language instruction. An association between an extension field and a machine language instruction may depend on the relative position of the extension field and the machine language instruction in the instruction packet.

Abstract: Control words are included in instruction packets to influence how one or more instructions in the packet are executed. Whether the control word is short or long will depend upon the situation. A short control word will be included in the packet in the event that the short control word has a sufficient number of content bits for support of a feature that influences how one or more instructions in the packet are executed. However, a long control word will be included in the packet instead of the short control word in the event that the short control word has an insufficient number of content bits for support of the feature and the long control word has a sufficient number of content bits for support of the feature.

Abstract: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Abstract: Data chunks are propagated through a write buffer from an input storage element to an output storage element by bypassing one or more intermediate storage elements of the write buffer.

Abstract: In a processor, a concatenation of contents of two registers having a fixed number of one-bit data storage elements are shifted by a software-defined, controllable amount and the fixed number of bits are selected from the shifted concatenation as output.

Abstract: A classification unit is to process an odd number of inputs in a single instruction cycle by comparing all distinct pairs of inputs and selecting one of the inputs based on the comparisons.

Abstract: A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second inputs and a carry-in bit. An output of the first adder is coupled to a first input of the third adder, and an output of the second adder is coupled to a second input of the third adder. The arithmetic circuitry is able to calculate an arithmetic operation on a set of four inputs. The arithmetic operation is fully determined by control bits and may be: an average of two values (with or without rounding by 1), an average of four values (with or without rounding by 1 or 2), or a sum of four values.