Abstract: A noise blanker (400) suitable for use with a radio receiver (500) having a track and hold unit (509) includes an impulse noise detector (401), a low pass filter (404) that is coupled to the impulse noise detector, and a first amplitude threshold detector (406) that is coupled to the output of the low pass filter and to the input of the track and hold unit. In one embodiment, this noise blanker is configured in conjunction with a radio receiver to yield a radio receiver that substantially minimizes the impact of noise impulses on resulting processed audio. In one embodiment, a second amplitude threshold detector (512) and a repetition rate threshold detector (513) are additionally utilized to allow gating of the internal signal processing paths of the radio receiver in conjunction with operation of the track and hold unit.

Abstract: A noise attenuation circuit (43) is provided for reducing noise in an RF stage of an AM radio receiver. A RF amplifier (44) amplifies an RF signal with amplitude modulated audio information from the signal path of an AM receiver. An AM detector (46) receives the amplified RF signal and removes the audio information. A high-pass filter (47) filters out a majority of the audio information. A noise pulse couples through the hi-pass filter (47) which is detected by a pulse detector (48) when above a predetermined threshold voltage. The pulse detector (48) enables an RF timer (49) for generating a pulse of a predetermined width. The RF timer enables a RF attenuator (51) for attenuating the RF signal in the signal path of the AM receiver. The RF attenuator (51) attenuates an average noise pulse to a level approximately equal to the magnitude of an unmodulated RF signal.

Abstract: A circuit for use in a phase locked loop (PLL) which is responsive to the PLL being out of lock for providing fast lock current to drive the VCO of the PLL in the direction to acquire lock. The circuit includes a pair of controlled current sources responsive to selective control signals for either sourcing or sinking fast lock current at the output of the circuit that are utilized to produce an error control voltage at the loop filter to drive the VCO accordingly while a reducing circuit is responsive to the control voltage reaching a predetermined value as the VCO is driven toward one end or the other of its range for clamping the control voltage while reducing the fast lock current to a reduced value thereby limiting excessive charge build-up on the loop filter capacitor of the PLL. Thus, the circuit permits the VCO to acquire fast lock up by providing fast lock current thereto while clamping the range of the VCO and reducing the fast lock current as the VCO approaches either end of its range.

Abstract: In an AM stereophonic receiver a voltage is developed in response to negative overmodulation in the received signal, to detection of a pilot tone, to detection of a minimum or no signal strength condition, and to external control. Predetermined levels of this voltage are utilized to enable/disenable various function circuits within the receiver to optimize the operation.

Abstract: A toggle flip-flop of the type which is controlled by a clock signal capable of assuming high and low states includes a master circuit portion and a slave circuit portion. The master circuit portion includes a first output stage which is latched when the clock signal is high while the slave circuit portion has an output stage which is latched when the clock signal is low. A driving voltage signal is produced in the slave circuit portion for driving the second output stage. Means are provided for inverting the driving voltage signal and for using the inverted version to drive the first output stage.