Patents by Inventor Roy Iggulden
Roy Iggulden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
Publication number: 20070267386Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.Type: ApplicationFiled: August 3, 2007Publication date: November 22, 2007Inventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang, Yun-Yu Wang -
Publication number: 20070158851Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Vincent McGahay, Ping-Chuan Wang, Yun-Yu Wang
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Publication number: 20070120259Abstract: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.Type: ApplicationFiled: January 31, 2007Publication date: May 31, 2007Inventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Stephen Loh, Ping-Chuan Wang
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POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
Publication number: 20060254053Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang, Yun-Yu Wang -
Publication number: 20060097394Abstract: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.Type: ApplicationFiled: November 4, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Stephen Loh, Ping-Chuan Wang
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Publication number: 20060073695Abstract: Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang
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Publication number: 20060066314Abstract: A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang
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Publication number: 20060001162Abstract: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.Type: ApplicationFiled: March 18, 2005Publication date: January 5, 2006Inventors: Ronald Schutz, Werner Robl, Rajeev Malik, Lawrence Clevenger, Oleg Gluschenkov, Cyril Cabral, Roy Iggulden, Yun-Yu Wang, Keith Wong, Irene McStay
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Publication number: 20050116342Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.Type: ApplicationFiled: December 28, 2004Publication date: June 2, 2005Inventors: Lawrence Clevenger, Ronald Filippi, Mark Hoinkis, Jeffery Hurd, Roy Iggulden, Herbert Palm, Hans Poetzlberger, Kenneth Rodbell, Florian Schnabel, Stefan Weber, Ebrahim Mehter
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Publication number: 20040155268Abstract: Methods and apparatus in accordance with the present invention may employ a layer of tungsten nitride having a ratio of nitrogen to tungsten that is below about 0.7 at and a layer of tungsten formed on the layer of tungsten nitride to obtain a conductive material.Type: ApplicationFiled: February 6, 2003Publication date: August 12, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Werner Robl, Roy Iggulden, Padraic Shafer, Keith Kwong Hon Wong
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Publication number: 20020016050Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.Type: ApplicationFiled: October 6, 1999Publication date: February 7, 2002Inventors: STEFAN J. WEBER, RONALD JOSEPH SCHUTZ, LARRY CLEVENGER, ROY IGGULDEN
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Patent number: 6252292Abstract: A vertically arranged fuse structure for a semiconductor device. A fuse stud is vertically arranged with respect to a major plane of the semiconductor device and adjacent and electrically connected to overlying electrically conducting material and underlying electrically conducting material. A fuse void is present in the vertically arranged fuse stud. In an unblown state, the fuse provides electrical connection between the overlying electrically conducting material and the underlying electrically conducting material. The electrical connection being breakable by passing electrical energy of a predetermined level through the fuse.Type: GrantFiled: June 9, 1999Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: Axel C. Brintzinger, Roy Iggulden, Stefan J. Weber, Peter Weigand
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Patent number: 6242789Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.Type: GrantFiled: February 23, 1999Date of Patent: June 5, 2001Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Stefan J. Weber, Axel Christoph Brintzinger, Roy Iggulden, Mark Hoinkis, Chandrasekhar Narayan, Robert Van Den Berg
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Patent number: 6218279Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.Type: GrantFiled: February 24, 2000Date of Patent: April 17, 2001Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Stefan J. Weber, Axel Christoph Brintzinger, Roy Iggulden, Mark Hoinkis, Chandrasekhar Narayan, Robert Van den Berg
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Patent number: 6136709Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein and placing the wafer in a deposition chamber. The method further includes depositing a metal on the wafer to fill the vias wherein the metal depositing is initiated when the wafer is at a first temperature and the depositing is continued while heating the wafer to a target temperature which is greater than the first temperature.Type: GrantFiled: October 6, 1999Date of Patent: October 24, 2000Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Sven Schmidbauer, Stefan J. Weber, Peter Weigand, Larry Clevenger, Roy Iggulden