Abstract: An output current control circuit (10) for use with CMOS output buffers so as to reduce significantly ground bounce noise, includes a variable resistance device (28) for limiting the maximum short circuit current in a pull-down transistor (N1) so as to reduce significantly ground bounce noise. A feedback resistor (R.sub.s) is used to sense a reference voltage developed at a system ground reference line (30) for controlling the resistance of the variable resistance device (28).

Abstract: A method for rapidly recovering the clock from Manchester-encoded signals using simple digital techniques is provided for use in an inexpensive Manchester-encoding receiver. The received Manchester-encoded signal is monitored to determine zero-voltage crossing. At each such crossing the frequency of the recovered clock is adjusted by comparing the occurrence of the zero-crossing with respect to the midpoint of the period of the presently-generated recovered clock. Shorten, center or lengthen adjustment signals are generated as a result of this comparison which are used to shorten or lengthen, by 1/16 increments of the inter-bit period of the received data signal, the period of the next-generated recovered-clock. The method is readily implemented as a sixteen-stage programmable counter providing a phase-locked loop.

Abstract: A signal pre-processing method for detecting valid Manchester-encoded activity on a line carrying Manchester-encoded data signals to an inexpensive Manchester-decoding receiver. Detection is provided by monitoring both a positive-level presence and a negative-level presence to determine whether the received Manchester-encoded signal exceeds a predetermined positive voltage or falls below a predetermined negative voltage. Following detection of such line activity, the received signal is determined to be validly Manchester-encoded if it first crosses a predetermined positive level or a predetermined negative level after having first previously crossed the opposite level within a time interval of 3/4 to 11/4 of the inter-bit period of the received data signals.

Abstract: A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.