Abstract: A utility monitor for detecting and storing power line disturbances is provided which includes peak-voltage sensing means for over-voltages which provides an interrupt signal at the time of a strobe pulse indicative of a voltage rise above a preset threshold and which removes the interrupt signal when said peak voltage drops a preselected amount below the preset threshold value. A peak-voltage sensing means for under-voltages is also included for obtaining an interrupt output at the time of said strobe pulse indicative of a voltage drop below a preset threshold and for removing the interrupt output when said peak-voltage rises a preset amount above the preselected threshold value. A preselected number of cycles of said input sinewave voltage are stored before and after said interrupt.

Abstract: An over-voltage interrupt circuit is provided which senses the local output of the phase controlled regulator. A reference is generated which is utilized in a comparator as the over-voltage threshold. When the sensed regulator output is above this threshold setting an override signal is produced which overrides the condition of the on/off control. The comparator is arranged to have a lower reset threshold value than the setting threshold so that the on/off control is again switched in response to the sensed voltage dropping below the reset threshold level. If the over-voltage condition persists, the comparator continues to set and reset and, accordingly, the on/off control is continually switched off and on giving a limited average voltage output from the regulator. The on/off control operates through a walk-in circuit which controls the voltge during turn on and off to prevent over and undershoot voltage problems.

Abstract: An improved ramp control circuit is provided for use in a three phase, SCR phase controlled, voltage regulator. Two, 180.degree. out of phase timing pulses are generated in a pair of comparators for each phase of the three phase input to the system. The comparator switching point is raised above the zero crossover point on each phase input by a voltage offset associated with each comparator. A logical circuit is driven by the predetermined combinations of the 180.degree. out of phase timing pulses from each of the pair of comparators to produce ramp timing pulses at each output of the logic circuit in accordance with the logic in the logical circuit. Each ramp timing pulse is utilized to generate a linear ramp, released and reset by the beginning and end, respectively, of each of said ramp timing pulses.