Abstract: An approach is disclosed for accomplishing redundancy in the central processor units of a remote multiplexer terminal (RMT). Through execution of a stored software program the RMT receives data from input/output devices, processes that data and transmits it to external equipment. The system uses two central processor units (CPU's), each with its own input/output (I/O) bus. Both CPU's actively and continuously monitor the status of the I/O subsystems. The software program designates one CPU as the "Master", the other CPU as the "Slave". The CPU designated as "Master" performs active control functions so long as error detection circuitry within each CPU determines that the operational status of the "Master" is good. Error detection is accomplished by incorporation of a "Watch Dog Timer" in each CPU. A failing CPU is redesignated to be a Slave (and is halted) and the previously designated Slave CPU is redesignated as a Master.

Abstract: A priority gating system is disclosed which is useful with a communication subsystem having a multiplicity of parallel input/output lines. To service these lines a priority address determination is made for all channels with 0 designating the highest priority and (n-1), the lowest in an n-channel system. Each signal line to the input/output devices will have a card select buffer serially inserted therein. All of the buffers will be enabled during the data transfer portion of the cycle. At the end of the service cycle for message transfer, the central processing unit initiates a dual pulse interrupt acknowledge command which first disables all buffers, then after a short delay, activates priority decoder circuitry. The priority decoder circuitry determines which of the n-channel input/output lines is to be serviced during the next data cycle.