Patents by Inventor Roy L. Scheuerlein

Roy L. Scheuerlein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5416371
    Abstract: A dynamic random access memory (DRAM) of 2/3 VDD precharge scheme is disclosed. A latch driving circuit controls the voltage of the common node of a sense latch so as to limit the downward voltage swing of bitlines to 1/3 VDD, a low level restore voltage. The sense latch is coupled to a pair of I/O data lines through PMOS FET column switches. This invention provides high speed memory operation and reduces power consumption.
    Type: Grant
    Filed: July 23, 1991
    Date of Patent: May 16, 1995
    Assignee: International Business Machines Corporation
    Inventors: Yasunao Katayama, Toshiaki Kirihata, Roy L. Scheuerlein