Abstract: Methods, systems, and devices for power envelope modification for memory systems based on time to thermal throttle are described. A memory system may dynamically change the power limit based on operating conditions associated with the memory system. For example, the memory system may measure the time before entering a thermal throttle mode. If the time is relatively short, the memory system may decrease the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to increase. Alternatively, if the time is relatively long, the memory system may increase the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to decrease.

Abstract: This disclosure is directed to a system for high efficiency storage in high capacity non-volatile solid state applications. The system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including receiving a request to program data, storing the data by default in a first type of storage with multi-level memory cells having a first number of levels, and bypassing a second type of storage with fewer levels. Upon detecting a condition, the processing device transfers the data to a third type of storage with a greater number of levels than the first type. This method optimizes storage efficiency and performance by dynamically managing data storage based on the portion of user logical block addresses that contain user data.

Abstract: This disclosure is directed to a system for high efficiency storage in high capacity non-volatile solid state applications. The system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including receiving a request to program data, storing the data by default in a first type of storage with multi-level memory cells having a first number of levels, and bypassing a second type of storage with fewer levels. Upon detecting a condition, the processing device transfers the data to a third type of storage with a greater number of levels than the first type. This method optimizes storage efficiency and performance by dynamically managing data storage based on the portion of user logical block addresses that contain user data.

Abstract: Methods, systems, and devices for methods for data prioritization in memory are described. A memory device may be configured to prioritize data such that high-priority data may remain in a cache to await operations while low-priority data may be transferred to higher-latency memory. For example, the memory device may receive a command to write data associated with one or more user operations to the memory system. The memory device may also receive an indication associated with the data that indicates to the memory device that the data is high priority. The memory device may store the data in a cache of the memory device to await operations. In response to a trigger, the memory device may transfer data not associated with the indication from the cache to multi-level memory cells (MLCs) of the memory device, such that the high-priority files may remain in the cache.

Abstract: Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.

Abstract: A method includes identifying and tracking host threads. A read command is received including a first logical block address (LBA). The first LBA and a first stored LBA in a cache are determined to share a spatial locality. The first LBA and the first stored LBA share a spatial locality when the first LBA is within a predetermined number of LBAs from the first stored LBA. The first stored LBA is removed from the cache responsive to the determination that the first LBA and the first stored LBA share the spatial locality. The first LBA is then added to the cache.

Abstract: Methods, systems, and devices for power envelope modification for memory systems based on time to thermal throttle are described. A memory system may dynamically change the power limit based on operating conditions associated with the memory system. For example, the memory system may measure the time before entering a thermal throttle mode. If the time is relatively short, the memory system may decrease the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to increase. Alternatively, if the time is relatively long, the memory system may increase the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to decrease.

Abstract: A processing device in a memory sub-system detects a power-on command for the memory device. The processing device obtains read information from a reference block of the memory device. The read information is based on reference data stored in the reference block. Based on the read information, the processing device determines an estimate of a duration for which the memory device was in a powered-off state. The processing device determines whether the duration satisfies a duration threshold, and responsive to determining the duration satisfies the duration threshold, the processing device initiates a folding operation for at least a subset of blocks of the memory device.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the cache. The cache has a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.

Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.

Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.

Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.

Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.