Patents by Inventor Roy M. Kim

Roy M. Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7519780
    Abstract: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jonathan J. DeMent, Roy M. Kim, Alvan W. Ng, Kevin C. Stelzer, Thuong Q. Truong
  • Publication number: 20080162823
    Abstract: Exemplary embodiments include a method for enhancing lock acquisition in a multiprocessor system, the method including: sending a lock-load instruction from a first processor to a cache; setting a reservation flag for the first processor, storing a reservation address, storing a shadow register number, and sending lock data to the first processor in response to the lock-load instruction; placing the lock data in target and shadow registers of the first processor; determining from the lock data whether lock is taken; resending the lock-load instruction from the first processor to the cache upon a determination that the lock is taken; determining whether the reservation flag is still set and its main memory address and shadow register number match with the saved reservation address and shadow register number for the first processor; sending a status-quo signal to the first processor without resending the lock data to the first processor upon a determination that the reservation flag is still set for the first p
    Type: Application
    Filed: January 2, 2007
    Publication date: July 3, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael N. Day, Charles R. Johns, Roy M. Kim, Peichun P. Liu
  • Publication number: 20080109585
    Abstract: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 8, 2008
    Inventors: Jonathan J. DeMent, Roy M. Kim, Alvan W. Ng, Kevin C. Stelzer, Thuong Q. Truong