Abstract: An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.