Abstract: A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself.

Abstract: A cache write back operation, write back modified data to memory from cache data array to fix inconsistency between them can be cancelled by the results of a comparison of the progress between a write back and snoop push or snoop kill operation. Write back is intended to make an empty slot to accommodate a reload data due to a cache miss and since a snoop push or snoop kill operation creates an invalid entry in the cache, write back is not needed. If simultaneous push or kill with write back operation exist, then write back machine is late cancelled. System performance improves due to preserving more cache lines in cache data array for possible future reuse.

Abstract: A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

Abstract: A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

Abstract: Initially, a SMI trap detects an application accessing a memory location associated with a physical hardware device. The SMI trap receives the device address for the address bus and compares that address with memory addresses for hardware devices being virtualized by virtual device simulators. If the address matches an available virtual device, the SMI caches the address, hooks and caches the corresponding IO instruction for the memory address and issues a SMI. A SMI handler receives the SMI and determines which virtual device simulator to call. Once activated by the SMI handler, the virtual device simulator interacts with the application and then returns control to the processor.

Abstract: A method and system for booting a user station in a computer network in which a first set of operating system information retrieved from the user station is used to attempt to boot the user station from a remote server. If the boot attempt fails, an iterative process is initiated in which a next set of operating system information is retrieved and used to attempt to boot the user station until a boot attempt is successful. Upon successfully booting the user station, the operating system information is modified to prioritize the set of information that resulted in a successful boot such that the successful set of information is selected first during a subsequent boot attempt. The operating system information may include a directory path of the remote server in which the user station attempts to locate an operating system kernel.

Abstract: A compact connector for a data processing system motherboard facilitates the performance of diagnostics on data processing system components. The connector includes first, second, and third terminals in communication with respective first, second, and third lines in the motherboard for serial port interrupts, system data, and keyboard interrupts, respectively. In an illustrative embodiment, the first and second lines comprise lines of an Industry Standard Architecture (ISA) bus, and the compact connector also includes a fourth terminal in communication with a fourth line in the motherboard for real-time-clock interrupts. This embodiment allows the motherboard to receive real-time-clock interrupts via the connector, so that a startup program of the data processing system may boot to an operating system that requires a real-time-clock. That operating system may then be utilized to test the motherboard.

Abstract: A mobile computing device and associated base stations are disclosed. The mobile computing device includes a system-on-chip (SOC) device that includes a general purpose processor core and a plurality of peripheral cells suitable for controlling a plurality of peripheral units. The mobile computing device further includes a system memory and a base unit interface. The base unit interface is suitable for connecting the mobile computing device to a base unit that includes a display adapter suitable for controlling a video display. The SOC is connected to and enabled to control the display adapter when the mobile computing device is connected to the base unit. The base unit interface may comprise a PCI interface that connects the SOC device to the base unit via a PCI bus. The plurality of peripheral units may include an audio adapter, a flash device, a wireless suitable for transmitting and receiving wireless information, and a liquid crystal display suitable for displaying text messages.

Abstract: Components and circuitry, including a common microprocessor, are combined into a single motherboard that is common to both a Personal Computer (PC) and a Network Computer (NC). The motherboard is capable of receiving a riser card. Riser cards specific to either a NC or a PC are designed to provide functions that are not present on the common motherboard. Connector slots such as Integrated Drive Electronics (IDE), Industry Standard Architecture (ISA) and Peripheral Component Interconnect (PCI) are available on a PC riser card to accommodate additional circuit boards. Devices such as a hard drive, CD ROM drive, etc., may be installed utilizing appropriate connectors on a PC specific riser card that are not required or available on the NC. A riser card for the NC will accommodate a compact flash card connector or various other expansion cards that provide functions specific to the NC.

Abstract: A computer network that includes a network server and a network client. The network server includes a storage medium configured with boot code data preferably comprising operating system software for the network client. The network client includes a power status indicator and is configured to query the power status indicator as part of a boot code sequence that is initiated in response to a boot event. The network client is configured to schedule retrieval of boot code data from the network server based upon the power status indicator. Preferably, the power status indicator includes a power fail circuit that indicates whether power to the network client has failed since a previous boot event. In one embodiment, the power fail circuit includes a flip flop arranged such that the output of the flip flop is preset when power is restored to the network client after a power failure. Preferably the clear input of the flip flop is programmably assertable.

Abstract: An apparatus and method, for use with a data processing system having an architecture, which provide for the possibility of smart card use without unduly impacting the data processing system's architecture. An enclosure, having at least one PC card acceptor and at least one smart card acceptor, is created. A suspension mechanism is operably connected to enclosure in a fashion such that suspension mechanism is capable of physically connecting enclosure to a motherboard such that enclosure is suspended above a component of motherboard. The method and system give rise to several advantages. One advantage is that board space is saved in that the enclosure is suspended over existing board components. A second advantage is that the method and system allow original equipment manufactures to make the provision of smart card usage optional, in that smart card usage can be provided by a simple add-on to lower-end systems.