Patents by Inventor Roy Perrigo

Roy Perrigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6871154
    Abstract: The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: March 22, 2005
    Assignee: LSI Logic Corporation
    Inventors: Jonathan Byrn, James Jensen, Roy Perrigo, Donald Gabrielson
  • Publication number: 20040254755
    Abstract: The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.
    Type: Application
    Filed: June 11, 2003
    Publication date: December 16, 2004
    Inventors: Jonathan W. Byrn, James A. Jensen, Roy Perrigo, Donald Gabrielson