Patents by Inventor Roy Prasad

Roy Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922182
    Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Google LLC
    Inventors: Roy Peterkofsky, William Earl, Martin Taillefer, Michael Dahlin, Chandra Prasad, Jaroslaw Kowalski, Anna Berenberg, Kristian Kennaway, Alexander Mohr, Jaidev Haridas
  • Patent number: 7743359
    Abstract: An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a second figure-of-merit of the photolithographic data set; and changing a second part of the photolithographic data set to increase the second figure-of-merit. The second computational model enables figure-of-merit calculations to be executed at a significantly faster execution rate than the first computational model.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: June 22, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad, Chi-Song Horng, Hsu-Ting Huang
  • Patent number: 7506300
    Abstract: A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein disrupting polygons includes any of the following polygon disruptions: breaking up, merging, or deleting polygons.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: March 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad
  • Patent number: 7444615
    Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: October 28, 2008
    Assignee: Invarium, Inc.
    Inventors: Gokhan Percin, Ram S. Ramanujam, Franz X. Zach, Abdurrahman Sezginer, Chi-Song Horng, Roy Prasad
  • Publication number: 20060266243
    Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
    Type: Application
    Filed: May 31, 2005
    Publication date: November 30, 2006
    Inventors: Gokhan Percin, Ram Ramanujam, Franz Zach, Abdurrahman Sezginer, Chi-Song Horng, Roy Prasad
  • Publication number: 20060248499
    Abstract: A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein disrupting polygons includes any of the following polygon disruptions: breaking up, merging, or deleting polygons.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: INVARIUM, INC.
    Inventors: Abdurrahman Sezginer, Roy Prasad
  • Publication number: 20060248498
    Abstract: An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a second figure-of-merit of the photolithographic data set; and changing a second part of the photolithographic data set to increase the second figure-of-merit. The second computational model enables figure-of-merit calculations to be executed at a significantly faster execution rate that the first computational model.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: Invarium, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad, Chi-Song Horng, Hsu-Ting Huang