Abstract: Data sharing among adjacent logic gates for shifting data in a multiplexer. Each logic gate implements two stages of shifting and provides for data sharing by connecting data inputs among the logic gates. Based upon the data sharing connections, control signals feed bits into each logic gate from adjacent logic gates to perform various shifting operations on a data bus.

Abstract: Several graphics processing elements are interconnected in a ring using a plurality of individual busses. Each bus interconnects a pair of the graphics processing elements and includes a like group of signal lines for transferring graphics command signals and information signals between graphics processing elements in the ring.

Abstract: An interface circuit included in a ring interconnected group of processing elements includes a backup FIFO to temporarily store information received by the interface circuit when it receives an indication that it temporarily should not forward information to the next processing element in the ring. The interface circuit can receive such an indication, for example, when it receives a signal from the downstream processing element in the ring indicating that the downstream circuit is unable to receive information, or when it receives an information packet requesting a read from the core of the processing element. When the interface circuit receives such an indication, it de-asserts an outgoing ready signal to the upstream processing element in the ring, which should cause the upstream processing element to stop sending information.

Abstract: An interface circuit receives both priority and non-priority information non-concurrently on a shared input bus during a first clock cycle and transmits the information received during the first clock cycle non-concurrently to a shared output bus during a second clock cycle following the first clock cycle. The received information includes status data identifying it as being either priority or non-priority information. All received information is provided to an external circuit via either a priority information path or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When the interface circuit is unable to transmit information, received information is backed up into either a priority or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information.

Abstract: A method for performing a division operation in a two-stage multiply pipeline apparatus by forming an approximate reciprocal R.sub.0 of the divisor D.sub.0, and calculating a first error term R.sub.1 by the equation R.sub.1 =1-R.sub.0 D.sub.0, and forming a second error term R.sub.2 =R.sub.1 *R.sub.1, and forming an approximate quotient N.sub.1 =R.sub.0 *N.sub.0.

Abstract: An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.