Abstract: A integrated circuit (IC) chip with ESD protection level and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and array pads are wired to I/O cells located on the chip. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection level. The design is then verified by first identifying the chip pads, I/O cells and ESD protect devices. Connections between these three structures are verified. Wires between the ESD protect devices and the chip pads and I/O cells are shrunk such that unsuitable connections becomes opens (disconnected) and are found in subsequent checking. Finally connections to guard rings are checked. Power rails are checked in a similar manner.

Abstract: A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.