Abstract: For example, an apparatus may include a scheduler configured to determine scheduling information to schedule radar transmissions of a radar device during a sequence of radar frames. For example, the scheduler may be configured to determine a burst-based frame setting to schedule a sequence of radar burst transmissions during a radar frame of the sequence of radar frames. In one example, the burst-based frame setting may include a setting of a burst gap duration. In one example, the burst gap duration may include a duration of a burst gap between first and second consecutive radar burst transmissions of the sequence of radar burst transmissions.

Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.

Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.