Abstract: A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more positive potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse. The disruption of the antifuse material is sensed and the programming pulse is extended for a fixed period of time following the disruption of the antifuse material. The programming pulse is followed by a soak pulse having a polarity having a polarity such that a more negative potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse.

Abstract: A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more positive potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse. The disruption of the antifuse material is sensed and the programming pulse is extended for a fixed period of time following the disruption of the antifuse material. The programming pulse is followed by a soak pulse having a polarity having a polarity such that a more negative potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.