Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for distributed processing in a vehicle networking system. A node in the vehicle networking system receives sets of processed sensor data from multiple nodes in the vehicle networking system. Each set of processed sensor data is generated using a first portion of a data processing algorithm on sensor data captured by different sets of sensors of the vehicle networking system. The node performs a second portion of the data processing algorithm based on the sets of processed sensor data received from multiple nodes, yielding a set of processed aggregated sensor data. The node may use the set of processed aggregated sensor data to provide a computer managed feature and/or transmit the set of processed aggregated sensor data to other nodes in the vehicle networking system.

Abstract: Various embodiments provide for data transmission using modulated carrier signals to carry data, where the carrier signal comprises a predetermined sequence of symbols. An embodiment can be used in such applications as data network communications between sensors (e.g., cameras, motion, radar, etc.) and computing equipment within vehicles (e.g., smart and autonomous cars).

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for determining diagnostic coverage for achieving functional safety. A diagnostic coverage determination system employs an optimized process for efficiently determining a diagnostic coverage level of an electronic circuit. The diagnostic coverage determination system generates an optimized netlist that includes a reduced number of nodes by applying one or more node reduction techniques. The diagnostic coverage is determined based on the optimized netlist, thereby reducing the number of nodes that are injected with faults.

Abstract: Various embodiments provide for using data encapsulation to extend support of an Audio Video Transport Protocol (AVTP) standard, which can be used in such applications as data network communications between sensors (e.g., cameras, motion, radar, etc.) and computing equipment within vehicles (e.g., smart and autonomous cars).

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for testing and characterization of computing systems implemented in vehicles. A testing system causes packet injectors in a vehicle networking system to execute a testing mode in which the packet injectors transmit synchronized sequences of data packets within the vehicle networking system. The testing system gathers, from logging mechanisms located within the vehicle networking system, diagnostic data describing data packet transmissions in the vehicle computer network during the testing mode. The diagnostic data includes data identifying data packets detected by the logging mechanisms and timestamps indicating times at which the data packets were detected by the logging mechanisms. The testing system generates, based on the diagnostic data and an expected diagnostic data, a testing report describing performance of the vehicle networking system during the testing mode.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for testing and characterization of computing systems implemented in vehicles. A testing system causes packet injectors in a vehicle networking system to execute a testing mode in which the packet injectors transmit synchronized sequences of data packets within the vehicle networking system. The testing system gathers, from logging mechanisms located within the vehicle networking system, diagnostic data describing data packet transmissions in the vehicle computer network during the testing mode. The diagnostic data includes data identifying data packets detected by the logging mechanisms and timestamps indicating times at which the data packets were detected by the logging mechanisms. The testing system generates, based on the diagnostic data and an expected diagnostic data, a testing report describing performance of the vehicle networking system during the testing mode.

Abstract: Various embodiments provide for data communications using decision feedback equalization (DFE) and Tomlinson-Harashima precoding (THP).

Abstract: Generally, a method and apparatus are disclosed that store sequential data units of a data packet received at an input port in contiguous banks of a buffer in a shared memory, thereby obviating any need for storing linkage information between data units. Data packets can extend through multiple buffers (next-buffer linkage information is much more efficient than next-data-unit linkage information). According to another aspect of the invention, buffer memory utilization can be further enhanced by storing multiple packets in a single buffer. For each buffer, a buffer usage count is stored that indicates the sum (over all packets represented in the buffer) of the number of output ports toward which each of the packets is destined.

Abstract: Roughly described, a packet switching fabric contains a separate queue scheduler for each combination of an input module and a fabric output port. The schedulers may also be specific to a single class of service. Each queue scheduler schedules its packets without regard to state of other input queues and without regard to packets destined for other output ports. In an aspect, the fabric manages per-flow bandwidth utilization of output port bandwidth capacity by monitoring the same and asserting backpressure toward the queue scheduler for any thread that is exceeding its bandwidth allocation. In another aspect, a switching fabric uses leaky buckets to apply backpressure in response to overutilization of downstream port capacity by particular subflows. In another aspect, a switching fabric includes a cascaded backpressure scheme.

Abstract: Roughly described, a packet switching fabric contains a separate queue scheduler for each combination of an input module and a fabric output port. The schedulers may also be specific to a single class of service. Each queue scheduler schedules its packets without regard to state of other input queues and without regard to packets destined for other output ports. In an aspect, the fabric manages per-flow bandwidth utilization of output port bandwidth capacity by monitoring the same and asserting backpressure toward the queue scheduler for any thread that is exceeding its bandwidth allocation. In another aspect, a switching fabric uses leaky buckets to apply backpressure in response to overutilization of downstream port capacity by particular subflows. In another aspect, a switching fabric includes a cascaded backpressure scheme.

Abstract: A repeater interface controller (“RIC”) integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted.

Abstract: A repeater interface controller ("RIC") integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted.

Abstract: A multi-media-access-controller (henceforth "multi-MAC") in accordance with this invention includes a plurality of transmit data path circuits and a plurality of receive data path circuits that respectively transmit and receive data serially on a corresponding plurality of network buses, a single transmit data path controller and a single receive data path controller that monitor status of and control operation of the respective transmit and receive data path circuits. Use of only two data path controllers eliminates the plurality of MACs used in prior art devices and therefore results in significant savings in die area. Use of a single CRC calculator also results in savings in die area.

Abstract: A LAN network switch includes a RAM forwarding database which contains the address-to-port mappings for all the workstations or other devices connected to the switch's plurality of ports and further includes at least one CAM-cache connected to respective one or more of the switch's ports. The CAM-cache, having an access time much faster than that of the forwarding database, stores selected ones of the address-to-port mappings. When it is desired for the switch to forward a packet, the destination address is extracted and the CAM-cache is accessed and searched. If the correct mapping is contained in the CAM-cache, the packet is immediately forwarded to the destination port without accessing the much larger and slower forwarding database. Only if the CAM-cache does not contain the correct mapping is the forwarding database accessed to retrieve the correct mapping.

Abstract: A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators.