Patents by Inventor Roy V. Prasad

Roy V. Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9292627
    Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Publication number: 20140068527
    Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Application
    Filed: October 28, 2013
    Publication date: March 6, 2014
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Dipankar PRAMANIK, Michiel Victor Paul KRUGER, Roy V. PRASAD, Abdurrahman SEZGINER
  • Patent number: 8572517
    Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: October 29, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Publication number: 20090307649
    Abstract: The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Patent number: 7318214
    Abstract: The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations. Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis. Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain photoresist parameters to be used in the patterning process.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Invarium, Inc.
    Inventors: Roy V. Prasad, Chi-Song Horng, Ram S. Ramanujam