Abstract: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.

Abstract: A rubidium frequency standard is compensated for frequency variations over temperature by allowing the rubidium frequency standard to vary while holding the output frequency constant. A voltage controlled crystal oscillator, locked to a physics package, provides the output signal. A temperature sensor senses temperature and proves a temperature signal to a microcontroller. A frequency synthesizer receives the output signal from the voltage controlled crystal oscillator as a reference and provides an RF signal to the physics package. The microcontroller looks up a frequency error in a memory in accordance with the temperature signal, generates an offset control word for the frequency synthesizer to compensate for the temperature and adjusts the VCXO with an error signal to compensate for temperature.

Abstract: An integrated frequency source with an integrated frequency standard and an integrated frequency synthesizer is disclosed. A voltage-controlled oscillator in the frequency standard is eliminated with a resulting improvement in phase noise. A reference frequency in the frequency standard is provided directly to the frequency synthesizer. The integrated frequency source is put on frequency over temperature by storing reference frequency errors over temperature in a lookup table, measuring the temperature, and calculating in a microprocessor synthesizer control data that offsets the synthesizer to compensate for reference frequency errors.

Abstract: A digital mixer employs a plurality of flip-flops to mix two digital input signals and provide a beat frequency output. The first input signal is provided as a clock signal to a first D flip-flop and to a third JK flip-flop. The second input signal is provided as a clock signal to a second D flip-flop. The inverted output of the first flip-flop is provided as a clock input to a fourth JK flip-flop. The non-inverted and inverted outputs of the second flip-flop are connected, respectively, to the J and K inputs of the third flip-flop. The non-inverted outputs of the second and third flip-flops are input to a first AND gate, the output of which connects to the J input of the fourth flip-flop. Likewise, the inverted outputs of the second and third flip-flops are input to a second AND gate, the output of which connects to the K input of the fourth flip-flop. The non-inverted output of the fourth flip-flop provides a beat frequency that is one-half the difference frequency of the two input signals.