Abstract: A medication delivery device comprising a base plate engaging a cover to form an interior, the interior including a pump drive mechanism for driving medication through the device, a drivetrain engaged to the pump drive mechanism, a magnetic encoder including an encoder hub mechanically coupled to the drivetrain, the encoder hub including a magnet, and a sensor that measures a magnetic field from the magnet to determine a rotational position of the drivetrain.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region.

Abstract: Tags representing characteristic terms in a set of matter-specific local documents, such as an accumulating litigation or medical record, are identified and used to evaluate the relevance to a user of each of a set of global, generally accessible documents. User-entered keywords and other parameters may also be incorporated into the search strategy to increase the relevance of returned documents.

Abstract: A control device, system and method for multi-pixel reading provides a processor receiving multi-pixel, uses memory units wherein each memory unit sequentially receiving a writing enable signal, and then receiving and storing multi-pixel. Simultaneously, the processor having multi-data bus receives multi-pixel of the each memory unit output. The clock of the enabling all the memory units is less than the delay of the processor reading, so that reducing the spare time of the image decoding system and reducing the reading time of the reading image.

Abstract: A chip with IDE host and IDE slave and corresponding self-debugging function is provided. The chip simplifies IDE debugging of a chip, which comprises a front-end and a backend, by offering separate debugging modes for an IDE host and an IDE slave on the same chip. The front-end provides output data of an internal IDE slave or output data of an external IDE slave in response to a host debug enable signal. The backend is coupled to the front-end. The backend provides functions of an internal IDE host according to the output data of the internal IDE slave or the external IDE slave, or directs the output data of the internal IDE slave to an external IDE host in response to a slave debug enable signal.

Abstract: A method and system for applying pipeline architecture to discrete cosine transform and inverse discrete cosine transform. Each of the discrete cosine transform and inverse cosine transform are divided into four phases computed by process elements. Each phase can be designed by adjusting the amount of process elements according the demand of performance.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.

Abstract: A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

Abstract: An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: A chip with IDE host and IDE slave and corresponding self-debugging function is provided. The chip simplifies IDE debugging of a chip, which comprises a front-end and a backend, by offering separate debugging modes for an IDE host and an IDE slave on the same chip. The front-end provides output data of an internal IDE slave or output data of an external IDE slave in response to a host debug enable signal. The backend is coupled to the front-end. The backend provides functions of an internal IDE host according to the output data of the internal IDE slave or the external IDE slave, or directs the output data of the internal IDE slave to an external IDE host in response to a slave debug enable signal.

Abstract: A control device, system and method for multi-pixel reading provides a processor receiving multi-pixel, uses memory units wherein each memory unit sequentially receiving a writing enable signal, and then receiving and storing multi-pixel. Simultaneously, the processor having multi-data bus receives multi-pixel of the each memory unit output. The clock of the enabling all the memory units is less then the delay of the processor reading, so that reducing the spare time of the image decoding system and reducing the reading time of the reading image.

Abstract: A method and device for sharing MPEG frame buffers utilizes a shared bidirectional frame buffer, which is used for temporarily storing bidirectional predicted pictures, to reduce the quantity of bidirectional frame buffers. And, through monitoring and controlling the displaying units and the decoding units, the method and device avoids the decoded image data overwriting the image data, which has not yet been displayed, in the shared bidirectional frame buffer.

Abstract: A device and a method of sharing IDCT are disclosed. Firstly, a data word and an identifier for representing which one of several formats are extracted from a received word. Then the data word is treated with IDCT to be a signed word afterward. Then the signed word is transformed into a formatted word between the values of a maximum value and a minimum value. The data word and identifier can be received by a word receiving means and treated with IDCT by an IDCT means to generate a signed word. The signed word is transformed into a formatted word for outputting via a word transforming means. Such that words with different formats can be treated with a sharing IDCT to save the redundant cost.

Abstract: A method and system for applying pipeline architecture to discrete cosine transform and inverse discrete cosine transform. Each of the discrete cosine transform and inverse cosine transform are divided into four phases computed by process elements. Each phase can be designed by adjusting the amount of process elements according the demand of performance.