Abstract: A JTAG standard test system or similar test system with additional circuitry which greatly reduces the number of test vectors required to verify the instruction decode logic. This is accomplished by capturing the decodes from a previous instruction such that they can be sent out within a few clock cycles rather than requiring the many thousands of clock cycles needed to verify that the decodes were doing that which they were supposed to do in accordance with the prior art procedures. Since most of the decode logic used by the instructions is common to other instructions, the effect of the logic only has to be verified by a single instruction using that part of the decode. Following that single verification, if the instruction decode test register is included, verification of the decode for following instructions can be accomplished by simply reading out the value held in the instruction decode test register of the invention.