Patents by Inventor Royce Yeoh Kao Tziat

Royce Yeoh Kao Tziat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device having multiple wire bonds for a bond area and methods thereof
    Patent number: 8791007
    Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Royce Yeoh Kao Tziat, Sally Yin Lye Foong
  • DEVICE HAVING MULTIPLE WIRE BONDS FOR A BOND AREA AND METHODS THEREOF
    Publication number: 20130134578
    Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: SPANSION LLC
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Royce Yeoh Kao Tziat, Sally Foong Yin Lye
  • Reduction of package height in a stacked die configuration
    Patent number: 7932131
    Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: April 26, 2011
    Assignee: Spansion LLC
    Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho
  • Reduction of package height in a stacked die configuration
    Publication number: 20090115033
    Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 7, 2009
    Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho