Patents by Inventor Roystein Oliveira

Roystein Oliveira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fault-tolerant architecture of flip-flops for transient pulses and signal delays
    Patent number: 7594150
    Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 22, 2009
    Assignees: Alcatel-Lucent USA Inc., Rutgers, The State University of New Jersey
    Inventors: Tapan Jyoti Chakraborty, Aditya Jagirdar, Roystein Oliveira
  • Soft error tolerant flip flops
    Patent number: 7482831
    Abstract: A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: January 27, 2009
    Assignees: Alcatel-Lucent USA Inc., Rutgers, The State University of New Jersey
    Inventors: Tapan Jyoti Chakraborty, Aditya Jagirdar, Roystein Oliveira
  • Soft error tolerant flip flops
    Publication number: 20070262787
    Abstract: A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Inventors: Tapan Chakraborty, Aditya Jagirdar, Roystein Oliveira
  • Fault-tolerant architecture of flip-flops for transient pulses and signal delays
    Publication number: 20070266282
    Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Inventors: Tapan Chakraborty, Aditya Jagirdar, Roystein Oliveira