Abstract: An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices. The system bus structure may be sized for a compact encasement and may carry as many as 129 simultaneous signals to and from various units connected to it. The system bus structure includes enabling structure for a centralized arbitration system, a centralized clock and synchronized transfer system, a centralized transfer monitor, a centralized parity error assessor and signalling system including transfer termination, and, a memory/inter-system inhibit system.

Abstract: A system for troubleshooting or debugging the various modules of a digital computer which are connected to the ports of a common system bus. A control unit transmits serial function and data codes to a serial bus link gate array whose parallel outputs are further processed to generate steering and clock commands. A first set of bus interface multiplexers are connected to each of the lines of the address, data and control fields of the system bus. A second set of multiplexers cause information represented by digital signals on selected ones of the lines in selected ones of the fields to be stored in a plurality of RAMs in response to the steering commands. A trigger logic is provided for selectively starting and stopping different clock signals in response to the clock commands.