Patents by Inventor Roza Kotlyar

Roza Kotlyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10396211
    Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Roza Kotlyar, Niloy Mukherjee, Charles C. Kuo, Uday Shah, Ravi Pillarisetty, Robert S. Chau
  • Publication number: 20190229264
    Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 25, 2019
    Inventors: Elijah V. KARPOV, Roza KOTLYAR, Prashant MAJHI, Jeffery D. BIELEFELD
  • Publication number: 20190181337
    Abstract: Disclosed herein are metal filament memory devices (MFMDs), and related devices and techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disposed between the electrode and the electrolyte, wherein the barrier material has a lower work function than the electrode.
    Type: Application
    Filed: September 25, 2016
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Roza Kotlyar, Prashant Majhi
  • Publication number: 20190115466
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: STEPHEN M. CEA, ROZA KOTLYAR, HAROLD W. KENNEL, GLENN A. GLASS, ANAND S. MURTHY, WILLY RACHMADY, TAHIR GHANI
  • Publication number: 20190051650
    Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
    Type: Application
    Filed: March 28, 2016
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Roza Kotlyar, Valluri R. Rao
  • Publication number: 20190043951
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
    Type: Application
    Filed: June 21, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Nicole K. Thomas, Ravi Pillarisetty, Payam Amin, Roza Kotlyar, Patrick H. Keys, Hubert C. George, Kanwaljit Singh, James S. Clarke, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts
  • Publication number: 20190044050
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.
    Type: Application
    Filed: March 6, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Kanwaljit Singh, Patrick H. Keys, Roman Caudillo, Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, James S. Clarke, Roza Kotlyar, Payam Amin, Jeanette M. Roberts
  • Publication number: 20190035893
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
  • Patent number: 10153372
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady, Tahir Ghani
  • Patent number: 10128356
    Abstract: Tunneling field effect transistors (TFETs) are described herein. In an example, a TFET includes a pocket disposed near a junction of a source region, wherein the pocket region is formed from a material having lower percentage of one type of atom than percentage of the one type of atom in source, channel, and drain regions.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Roza Kotlyar, Ian A. Young
  • Publication number: 20180323195
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Application
    Filed: December 3, 2015
    Publication date: November 8, 2018
    Applicant: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys
  • Patent number: 10115822
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Roza Kotlyar, Kelin Kuhn
  • Patent number: 10109711
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Anand S Murthy, Glenn A Glass, Kelin J Kuhn, Tahir Ghani
  • Publication number: 20180226509
    Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
    Type: Application
    Filed: July 31, 2015
    Publication date: August 9, 2018
    Applicant: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Roza Kotlyar, Niloy Mukherjee, Charles C. Kuo, Uday Shah, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 9972686
    Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros
  • Patent number: 9935107
    Abstract: Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Kelin J Kuhn, Tahir Ghani
  • Patent number: 9911835
    Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios, Anurag Chaudhry, Thomas D. Linton, Jr., Ian A. Young, Kelin J. Kuhn
  • Patent number: 9893149
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Patent number: 9876014
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Patent number: 9871106
    Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Roza Kotlyar, Gilbert Dewey, Benjamin Chu-Kung, Ian A. Young