Abstract: A computer system includes a processor that operates in a normal world and a secure world and that provides hardware-level isolation between the normal world and the secure world. A storage device of the computer system has a protected data region that stores critical data. A random-access memory of the computer system has a normal memory space that is accessible in the normal world and a secure memory space that is accessible only in the secure world. The secure memory space stores commands that transfer the critical data between the protected data region and the normal memory space by direct memory access.

Abstract: A graceful shutdown of a computer system is initiated by sending a command to an asynchronous dynamic random access memory refresh (ADR) trigger device to assert an ADR trigger. Responsive to the command, the ADR trigger device asserts the ADR trigger to initiate an ADR of a non-volatile dual in-line memory module (NVDIMM) of the computer system. In response to the ADR trigger being asserted by the ADR trigger device, an ADR of the NVDIMM is performed before completing the graceful shutdown of the computer.

Abstract: A semiconductor device with an embedded PCI 2.1 compliant bridge provides expanded functionality as system-level implementations of a PCI-to-PCI bridge, and enhances the level of integration possible. The embedded PCI-to-PCI bridge allows the creation of multi-function, multimedia add-on cards supporting multiple devices. Multi-function, multimedia subsystems that provide audio, graphics, MPEG, etc., are mapped into a bridged-to PCI-bus that keeps such traffic off the main PCI-bus. The advantage for the system or add-in card vendor is that the various multimedia chips that are combined can come from different sources, providing an optimized and highly customized combination of functions.

Abstract: A transparent direct memory access method comprises emulating an ISA-bus mapped direct memory access controller (ISA-DMAC) with a PCI-bus mapped direct memory access controller (PCI-DMAC). The ISA-DMAC exists, but there may not actually be any resources mapped into the ISA-bus space. Write snooping by the PCI-DMAC of a PCI-bus processor detects whenever an attempt is made to write the ISA-DMAC, and copies the data written into the ISA-DMAC registers into a corresponding register of the PCI-DMAC. The direct memory access operation commanded by the PCI-bus processor of the ISA-DMAC is performed by the PCI-DMAC in the PCI-bus resource space. When the direct memory access operation is completed, the PCI-DMAC updates its registers and does a write back to update the ISA-DMAC registers. The PCI-bus processor can then read the PCI-DMAC directly for status, or if legacy software is running the ISA-DMAC will respond with the appropriate register value.