Patents by Inventor Ru-Chian Chiang

Ru-Chian Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming novel BARC open for precision critical dimension control
    Patent number: 7265056
    Abstract: A method for forming an opening in a semiconductor device is provided. In one embodiment, a bottom anti-reflective coating (BARC) layer is formed overlying an insulation layer of a substrate. A patterned photoresist layer including at least one opening therein is formed overlying the BARC layer.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Huan Tsai, Ru Chian Chiang, Hun Jan Tao
  • Borderless interconnection process
    Patent number: 6878639
    Abstract: A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: April 12, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Ru-Chian Chiang, Hun-Jan Tao
  • BORDERLESS INTERCONNECTION PROCESS
    Publication number: 20050064721
    Abstract: A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 24, 2005
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Ru-Chian Chiang, Hun-Jan Tao