Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

Abstract: A semiconductor device with different isolation structures and a method of fabricating the same are disclosed. The a method includes forming first and second fin structures on a substrate, forming a dummy fin structure on the substrate and between the first and second fin structures, forming a polysilicon structure on the dummy fin structure, forming source/drain regions on the first and second fin structures, and replacing the polysilicon structure with a dummy gate structure. A top portion of the dummy gate structure is formed wider than a bottom portion of the dummy gate structure.

Abstract: Interconnect structures can include a capacitor of specified structure and/or a guard ring which surrounds a capacitor. The capacitor may include a bowed region with an expanded width that permits the inclusion of a void containing air or another gas. Alternatively, the capacitor may be an MIM capacitor or an MIMIM capacitor having a vertical trench and horizontal plates and formed from conformal layers. The guard ring reduces noise which may damage the capacitor. Any combination of these three features may be used to improve capacitance and reliability.

Abstract: Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

Abstract: Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

Abstract: The present disclosure provides an image sensor and a method of manufacturing the same. The image sensor includes a substrate and a gate electrode. The gate electrode is disposed proximate to a first side of the substrate. The gate electrode includes a first gate portion, a second gate portion, and a third gate portion. The first gate portion is disposed over the first side of the substrate. The second gate portion is disposed within the substrate and connected to the first gate portion. The third gate portion is disposed below and connected to the second gate portion. A first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a fin structure protruding from between adjacent portions of the isolation region, the fin structure including a plurality of fins and a mesa, a channel region of the fin structure having a first portion in the fins and having a second portion in the mesa, the fins and the mesa being a continuous semiconductor material, the mesa having a greater width than the fins; and a first gate structure on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and extending along the second portion of the channel region in the mesa.

Abstract: A semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed over the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, where the first gate extension has a first depth measured from a top surface of the substrate. The semiconductor structure further includes a second gate extension protruding from the gate structure into the second isolation structure, where the second gate extension has a second depth that is different from the first depth.

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes a first region including a gate electrode disposed over a semiconductor fin, a second region, and a border region disposed between the first and second regions. The border region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed over the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. A top surface of the second conductive layer and a top surface of the gate electrode may be substantially co-planar.

Abstract: A method is provided. The method includes determining a first hotspot region of a contact structure map. The method includes enlarging, according to a first predefined enlargement profile, the first hotspot region to determine a first enlarged region of the contact structure map. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cropped region, of the contact structure map, that excludes the first portion of the first enlarged region. The method includes updating a first patterned oxide layer map based upon the cropped region to generate an updated patterned oxide layer map.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.

Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.

Abstract: A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

Abstract: A metal layer of a semiconductor device may be included in an extreme low dielectric constant (ELK) dielectric layer in an interconnect structure of the semiconductor device. The metal layer may be coupled with a bonding via that extends through a silicon carbide (SiC) layer in a bonding region of the semiconductor device. The ELK dielectric layer and/or the silicon carbide layer reduces stress migration in the semiconductor relative to the use of other dielectric materials such as silicon nitride and/or silicon glass. The ELK dielectric layer and/or the silicon carbide layer also reduces resistance-capacitance (RC) delay in the interconnect structure relative to the use of other dielectric materials. The ELK dielectric layer and/or the silicon carbide layer provides improved adhesion with the metal material(s) (e.g., copper and/or another metal material) of the metal layer and/or of the bonding via coupled with the metal layer.