Abstract: The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A modified polyurethane material and a method for manufacturing the same are provided. A dianhydride is added into an aliphatic diisocyanate to form a liquid reactant. A solvent is absent from the liquid reactant. An oligomerization is implemented onto the liquid reactant so as to form an oligomer having a terminal isocyanate group. A polyol and a curative are added into the oligomer having the terminal isocyanate group for a polymerization so as to form the modified polyurethane. Based on a total weight of the modified polyurethane being 100 wt %, a content of a hard segment of the modified polyurethane ranges from 15 wt % to 45 wt %.

Abstract: Provided herein are subunit vaccine compositions comprising a nanocarrier and a lipid antigen, a peptide antigen or combinations thereof that elicit bother a CD1-restricted and an MHC-restricted T cell response in a subject. Methods for making and using the subunit vaccine compositions are also provided.

Abstract: A computing device obtains a to-be-processed video frame sequence of a first resolution. For each to-be-processed video frame in the to-be-processed video frame sequence, the computing device: (i) performs resolution reconstruction according to a resolution reconstruction model so as to obtain an initial reconstructed video frame of a second resolution, (ii) determines a contour region in the initial reconstructed video frame; and (iii) performs contour enhancement on the contour region to obtain a target reconstructed video frame. The computing device generates a reconstructed video frame sequence of the second resolution according to a plurality of target reconstructed video frames corresponding to the plurality of to-be-processed video frames.

Abstract: A posture comparison method, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining M first image frames of a first video stream within a specific time interval, and obtaining N second image frames of a second video stream within the specific time interval; determining K first joint points corresponding to K specified joints in each first image frame, and determining K second joint points corresponding to the K specified joints in each second image frame; obtaining an m-th first image frame among the M first image frames and an n-th second image frame among the N second image frames; and determining a difference between each first joint point and each corresponding second joint point in the m-th first image frame and the n-th second image frame, and determining a posture difference degree and providing a posture correction recommendation corresponding to the specific time interval accordingly.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Abstract: Provided is an inverter, comprising a conversion module, a delivering module, an inductance module, and a communication module. The delivering module and the inductance module are separately connected to the conversion module by means of plug-in, and the communication module is electrically connected to the delivering module, the conversion module, or the inductance module by means of plug-in. The electrical connection between the modules inside the inverter can be realized by means of plug-in, such that the electrical connection between the modules is more convenient, the working efficiency and maintenance efficiency of electrical connection are improved, and the influence of the electromagnetic interference, which is occurred when the modules are connected by means of wires, on the working stability of the modules can be avoided, thereby ensuring the working stability of the inverter.

Abstract: An example methodology implementing the disclosed techniques includes, by a computing device, generating a demand-based forecast for a part and generating an active service unit (ASU)-based forecast for the part based on a field incident rate of the part. The method also includes determining an optimal weight to apply to the demand-based forecast and the ASU-based forecast for the part, the optimal weight being based on a plurality of estimated optimal weights of historical parts for which lifecycle demand is known, the plurality of estimated optimal weights of the plurality of historical parts being indicative of dependency of demand-based forecasts and ASU-based forecasts to actual demand for the plurality of historical parts. The method further includes combining the demand-based forecast and the ASU-based forecast for the part using the optimal weight determined for the part, wherein the combining generates a rest-of-lifecycle demand forecast for the part.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Abstract: A non-transitory computer readable medium is described. The non-transitory computer readable medium has computer executable instructions that when executed cause a processor to: determine a diabetic retinopathy prediction based at least in part on a weighted sum of at least five patient predictors in a database storing at least one patient record having first data; and pass an alert to a user responsive to the diabetic retinopathy prediction being within a predetermined range.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.

Abstract: The present invention provides a method for OSA (Obstructive Sleep Apnea) severity classification by using recording-based Peripheral Oxygen Saturation Signal. The major feature of the present invention emphasizes on using a recording-based Peripheral Oxygen Saturation Signal (SpO2 signal) as an input, which is different from the deep learning-based prior art of using segment-based signals as an input to a model, and the segment-based signals has only two classification results, i.e. normal or apnea.