Patents by Inventor Ru-Yu WANG
Ru-Yu WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230124337Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
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Publication number: 20230111939Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
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Publication number: 20230042514Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.Type: ApplicationFiled: January 21, 2022Publication date: February 9, 2023Inventors: Ru-Yu WANG, You-Cheng XIAO, Kao-Cheng LIN, Pin-Dai SUE, Ting-Wei CHIANG
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Patent number: 11552085Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.Type: GrantFiled: September 28, 2020Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng Xiao, Jhih-Siang Hu, Ru-Yu Wang, Jung-Hsuan Chen, Ting-Wei Chiang
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Publication number: 20220359002Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsin NIEN, Wei-Chang ZHAO, Chih-Yu LIN, Hidehiro FUJIWARA, Yen-Huei CHEN, Ru-Yu WANG
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Publication number: 20220302136Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.Type: ApplicationFiled: August 17, 2021Publication date: September 22, 2022Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
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Patent number: 11404113Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.Type: GrantFiled: September 28, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
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Publication number: 20220102363Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
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Publication number: 20210398589Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.Type: ApplicationFiled: September 28, 2020Publication date: December 23, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsin NIEN, Wei-Chang ZHAO, Chih-Yu LIN, Hidehiro FUJIWARA, Yen-Huei CHEN, Ru-Yu WANG