Abstract: A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.

Abstract: A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.

Abstract: A topology for optical transceiver components comprises an electrical signal interface stage, a data timing and signal reformatting stage, and an optical fiber interface stage. Unlike transceiver components known in the art, functions having signals with the most jitter are partitioned into the electrical signal interface stage. Data timing functions, for example retiming or clock and data recovery, are included in the data timing and reformatting stage. Output jitter from the data timing and signal reformatting stage is approximately equal to jitter in a clock signal, enabling use of semiconductor components having jitter greater than SONET limits and thereby increasing a value of production yield. Embodiments of the invention are well suited for 40 G transmitters and receivers in nonconnectorized surface mount packages. 40 G transceivers built in accord with the invention are expected to have lower cost, smaller size, and higher production yield than 40 G transceivers known in the art.

Abstract: A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.

Abstract: A transponder having a dynamic remapping circuit remaps a value of decision threshold voltage Vdtc and a value of optical power RXP to a reference voltage Vref to minimize the bit error rate BER of a communication system. The dynamic remapping circuit implements a bilinear mapping of Vdtc and RXP to Vref with three bilinear remapping constants “a”, “b”, and “c” selected to align a remapped value of Vdtc_opt to a selected Vdtc normalization value, Vdtc_norm. A transponder in accord with an embodiment of the invention prevents BER from exceeding a threshold value of BER whether RXP or OSNR, or both, remain constant, change continuously, or change intermittently. Constants “a”, “b”, and “c” are related to parameters resulting from mathematically fitting a line to data comprising Vdtc_opt versus RXP. Another embodiment comprises a method for dynamically optimizing Vdtc and RXP to Vref in a transponder with a bilinear remapping circuit.

Abstract: A topology for optical transceiver components comprises an electrical signal interface stage, a data timing and signal reformatting stage, and an optical fiber interface stage. Unlike transceiver components known in the art, functions having signals with the most jitter are partitioned into the electrical signal interface stage. Data timing functions, for example retiming or clock and data recovery, are included in the data timing and reformatting stage. Output jitter from the data timing and signal reformatting stage is approximately equal to jitter in a clock signal, enabling use of semiconductor components having jitter greater than SONET limits and thereby increasing a value of production yield. Embodiments of the invention are well suited for 40 G transmitters and receivers in nonconnectorized surface mount packages. 40 G transceivers built in accord with the invention are expected to have lower cost, smaller size, and higher production yield than 40G transceivers known in the art.

Abstract: A method and system for photodetector packaging system is provided with a insulating substrate having a shoulder section and a wire bond is used for coupling the photodetector to the insulating substrate at the shoulder section. The system includes an optical fiber that directs incident light directly to the photodetector. Also provided is a method and system for packaging photodetectors with a insulating substrate using conducting vias and a wire bond to couple the photodetector to the insulating substrate. The system includes conducting tabs that are coupled to the conducting vias. The metal tabs are coupled with a transimpedance amplifier by wire bonds and the transimpedance amplifier is coupled to a limiting amplifier by wire bonds.

Abstract: A system and process is provided for packaging optical-electronic components used in fiber-optics networks. A top lid with an opening covers all the components of the optical-electronic package. A fiber boot with a groove is provided, wherein the opening in the top lid mates with the fiber boot groove. The fiber boot groove is located between plural shoulders. An optical fiber passes through an opening in the fiber boot and is firmly held within the fiber boot.

Abstract: A system and apparatus for packaging a laser diode is provided according to the present invention. It includes a solid structure having a first cavity, wherein the first cavity receives a fiber pipe with optical fiber, which is aligned to the laser diode. The solid structure also includes a recess that receives the fiber pipe; and a step for receiving a sealing ring. The solid structure is multi-layered and may be manufactured from ceramic material, beryllium oxide or aluminum nitride. The solid structure includes a second cavity that accommodates a fiber alignment mechanism; a sub-mount on which the laser diode is placed; and/or heat sink used for conducting heat from the laser diode.