Abstract: A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.

Abstract: An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

Abstract: A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.

Abstract: A multi-channel remote keyless entry (RKE) transponder having dynamically re-configurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bi-directional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract: An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

Abstract: An internal voltage regulator in an integrated circuit device is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator protects the low voltage core logic circuits of the integrated circuit device from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory may be part of and operational with the low voltage core logic circuits for storing device operating parameters. Therefore, the internal voltage regulator also protects the low voltage nonvolatile memory from excessive high voltages. Once the integrated circuit device has stabilized and all logic circuits therein are fully function, a bit(s) in the nonvolatile memory may be read to determine if the internal voltage regulator should remain active, e.g., how power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device is powered by a low voltage.

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract: A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode to provide for a first output signal at the first pin and an inverted first output signal at the second pin.

Abstract: A time signal receiver and decoder receives, detects and stores time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.

Abstract: A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q loading circuit coupled to the tank circuit of the regenerative amplifier. The amplitude detector turns on the Q loading circuit which then stops the regenerative amplifier from oscillating, and the Q-loading remains on for a brief time to insure that the regenerative amplifier has stopped oscillating. After the brief time, the Q loading circuit is turned off and the regenerative amplifier goes into oscillation again. This cycle repeats controllably over and over, resulting in a lower self-induced noise floor and improved received signal sensitivity.

Abstract: A multi-channel remote keyless entry (RKE) transponder having dynamically re-configurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bi-directional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.

Abstract: A bidirectional remote keyless entry (RKE) transponder comprises an analog front-end (AFE) having a programmable wake-up filter that predefines the waveform timing of the desired input signal, minimum modulation depth requirement of input signal, and independently controllable channel gain reduction of each of its three channels, X, Y, and Z. The wake-up filter parameters are the length of high and low durations of wake-up pulses that may be programmed in a configuration register. The wake-up filter allows the AFE to output demodulated data if the input signal meets its wake-up filter requirement, but does not output the demodulated data otherwise. The AFE output pin is typically connected to an external device for control, such as a microcontroller (MCU). The external device typically stays in low current sleep (or standby) mode when the AFE has no output and switches to high current wake-up (or active) mode when the AFE has output.

Abstract: An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes.

Abstract: A time signal peripheral may include a radio receiver, decoder/demodulator and time registers. The time signal peripheral may receive, detect and store time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. A digital processor may be coupled to and control the time signal peripheral. The digital processor may be used to decode the time information in the received time signal, store the decoded time information and make the time information available for use by a device and/or system, or the time signal peripheral may do these functions, allowing the digital processor to be used for higher level applications. The time signal peripheral may be fabricated on an integrated circuit die with or without the digital processor.

Abstract: A time signal receiver and decoder receives, detects and stores time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.

Abstract: A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q loading circuit coupled to the tank circuit of the regenerative amplifier. The amplitude detector turns on the Q loading circuit which then stops the regenerative amplifier from oscillating, and the Q-loading remains on for a brief time to insure that the regenerative amplifier has stopped oscillating. After the brief time, the Q loading circuit is turned off and the regenerative amplifier goes into oscillation again. This cycle repeats controllably over and over, resulting in a lower self-induced noise floor and improved received signal sensitivity.

Abstract: An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes.

Abstract: The present invention is directed to an apparatus and method of increasing the sensitivity of a magnetic sensor embedded in a key fob used in passive keyless entry and identification systems. The sensitivity of the sensor is increased by magnetically coupling a pair of magnetic flux concentrators at opposite ends of the magnetic core of the sensor, which is surrounded by a helical conductive coil. Addition of the magnetic flux concentrators external to the coil effectively forces a larger window of magnetic flux through the coil than was possible without them. This increases the magnetic sensitivity of the coil as a sensor in a time varying magnetic field. In a key fob/passive keyless device this results in an increased range of operation.

Abstract: Evaluation and optimization of a magnetic sensor embedded in a key-fob transponder used in a passive keyless entry system is achieved with a test circuit comprising a signal generator and coil from which a time varying amplitude magnetic field is generated. The magnetic sensor is placed in the magnetic field and the frequency-amplitude characteristics are determined by varying the frequency of the signal generator. Orientation of the magnetic sensor with the magnetic field is also determinative of the characteristics and operation of the sensor. A simulated load and signal strength indicator is temporarily coupled to the output of the magnetic sensor during evaluation of how the sensor will function when connected to the normal input circuits of the PKE transponder.