Patents by Inventor Rubayat Mahmud

Rubayat Mahmud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated WLUF and SOD process
    Patent number: 9728515
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • INTEGRATED WLUF AND SOD PROCESS
    Publication number: 20160247774
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • Integrated WLUF and SOD process
    Patent number: 9349698
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar
  • INTEGRATED WLUF AND SOD PROCESS
    Publication number: 20140001631
    Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Inventors: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar