Abstract: High-level synthesis (HLS) is a complex design flow that exploits the benefit of modern language features such as loops, inheritance, templates, etc. for rapid prototyping of hardware designs. Hardware engineers explore various design space parameters in a time-consuming trial-and-error approach to meet a target design specification. This invention provides a framework where machine learning methods are integrated with Bayesian optimization (BO) to accelerate hardware design in HLS. This tool is built around the context of HLS pragma exploration and kernel transformation. It can produce best set of pragma installments to determine parameters by optimizing on multi-objective functions, such as reduction of digital signal processor, flip-flop, look-up table, power consumption, and latency. The method uses classical deep neural network and quantum neural network for reinforcement meta learning to predict the synthesis characteristics and synthesizability under a given time budget.