Abstract: A method for checking an output signal of a timer module is provided, the timer module having at least one output module, at least one input module, and at least one logic module. The output signal to be checked is read in into the timer module via an input module in addition to its output via an output module, and in the input module, signal characteristics to be checked are determined for the output signal to be checked. Furthermore, the signal characteristics to be checked are read by the logic module from the input module and the signal characteristics to be checked are compared in the logic module to the predefined values for the signal characteristics.

Abstract: A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit.

Abstract: A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A hardware data processing unit has at least one base transmitter module, at least one logic unit, and at least one routing unit. The base transmitter module provides base values of a physical variable. The routing unit arbitrates a group of data nodes associated therewith in a determined sequence. The duration of a cycle is defined by a complete iteration of the determined sequence. The hardware data processing unit has a mechanism that checks the cycle duration. The mechanism carries out a first blocked access to a determined data node of the group to capture and store a first base value from the base transmitter module. The mechanism carries out a second blocked access to the determined data node to capture and store a second base value. The mechanism determines a difference between the first and the second base values.

Abstract: In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed.

Abstract: A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

Abstract: A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit.

Abstract: A method for checking an output signal of a timer module is provided, the timer module having at least one output module, at least one input module, and at least one logic module. The output signal to be checked is read in into the timer module via an input module in addition to its output via an output module, and in the input module, signal characteristics to be checked are determined for the output signal to be checked. Furthermore, the signal characteristics to be checked are read by the logic module from the input module and the signal characteristics to be checked are compared in the logic module to the predefined values for the signal characteristics.

Abstract: In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink.