Patents by Inventor Ruben Gonzalez Garcia

Ruben Gonzalez Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Prediction based instruction steering to wide or narrow integer cluster and narrow address generation
    Patent number: 7380105
    Abstract: A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 27, 2008
    Assignee: The Regents of the University of California
    Inventors: Alexander V. Veidenbaum, Adrian Cristal Kestelman, Mateo Valero Cortes, Ruben Gonzalez Garcia
  • ASYMMETRIC CLUSTERED PROCESSOR ARCHITECTURE BASED ON VALUE CONTENT
    Publication number: 20070294507
    Abstract: A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, UNIVERSITAT POLITECNICA DE CATALUNYA
    Inventors: ALEXANDER V. VEIDENBAUM, ADRIAN CRISTAL KESTELMAN, MATEO VALERO CORTES, RUBEN GONZALEZ GARCIA