Patents by Inventor Ruben Herrera

Ruben Herrera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6882198
    Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 19, 2005
    Assignee: Agere Systems Inc.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Publication number: 20040056696
    Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.
    Type: Application
    Filed: July 8, 2003
    Publication date: March 25, 2004
    Applicant: Agere Systems Inc.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Patent number: 6621319
    Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 16, 2003
    Assignee: Agere Systems Inc.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Publication number: 20030042936
    Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Inventor: Ruben Herrera
  • Patent number: 6525574
    Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: February 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Ruben Herrera
  • Publication number: 20020180528
    Abstract: A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 5, 2002
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ruben Herrera, Sanjeev Ranganathan
  • Patent number: 6480065
    Abstract: A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: November 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ruben Herrera, Sanjeev Ranganathan
  • Patent number: 6292023
    Abstract: A finite state machine in which n discrete states of the machine are encoded using a set of n bistable elements permitting simplified decoding of states. Transitions between discrete states are illustratively executed by selectively directing a bistable device to a 1 state using transition circuits activated by positive transitions of asynchronous spiking inputs. In one illustrative embodiment the positive transition is capacitively coupled to a switch that connects the complement output of a bistable element to ground, thereby causing the nominal output of that element to approach a voltage corresponding to a 1 state. In a second illustrative embodiment a pass transistor combination maintains a capacitor at the nominal output voltage of the bistable element in a 1 state until a spiking input signal arrives. A combination of the spiking input signal and the voltage on the capacitor connects the complement output of another bistable element to ground, thus switching that other bistable element.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 18, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Ruben Herrera, Rahul Sarpeshkar