Abstract: A knife having a hook incorporated into the blade for skinning, wherein the hook is a belly hook that is positioned on the belly side or under side of the knife opposite a finger guard area. Methods of the using the knife include steps for using the cutting edge to cut and using the hook to cut by pressure applied away from the user's body.

Abstract: A knife having a hook incorporated into the blade for skinning, wherein the hook is a belly hook that is positioned on the belly side or under side of the knife opposite a finger guard area. Methods of the using the knife include steps for using the cutting edge to cut and using the hook to cut by pressure applied away from the user's body.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material.

Abstract: Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.

Abstract: An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material.

Abstract: An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.

Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Abstract: A semiconductor die package including a semiconductor die including a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: One embodiment of the invention is directed to a semiconductor die package including a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.