Abstract: A voltage balancing circuit includes a direct-current-to-direct-current (DC-to-DC) voltage converter interconnecting a first battery having a first voltage and a second battery having a second voltage, wherein the DC-to-DC converter transfers electrical power from the first battery to the second battery when the first voltage is greater than the second voltage, and transfers electrical power from the second battery to the first battery when the first voltage is less than the second voltage, and wherein the transfer of electrical power from the first battery to the second battery or from the second battery to the first battery balances the electrical power difference between the first battery and the second battery.

Abstract: A voltage converter includes a converter stage having a direct current to direct current (DC-to-DC) voltage converter, wherein the converter stage receives a first DC voltage and outputs a second DC voltage different than the first DC voltage. The voltage converter also includes a boost pre-stage having a boosting circuit and a capacitor, wherein the boost pre-stage receives a DC voltage from a battery and outputs a boosted DC voltage to the converter stage as the first voltage, wherein the boosted DC voltage is greater than the DC voltage from the battery. The boosted DC voltage of the boost pre-stage output to the converter stage provides fault resistant operation of the converter stage in the event of one or more fluctuations in an operating range of the DC voltage from the battery.

Abstract: In at least one embodiment, a battery charger is provided. The battery charger includes at least one transformer, a first active bridge, a second active bridge, and a pulsating buffer (PB) converter. The first active bridge is positioned on a first side of the transformer to provide a first voltage signal based on an input voltage signal from a mains supply of an electrical grid. The second active bridge is positioned on a second side of the transformer to provide a second voltage signal to store on one or more batteries based on the first voltage signal. The PB converter includes a plurality of switching devices to interface with the second active bridge to modify the second voltage signal. The plurality of switching devices provide a voltage for storage on at least one capacitor of the PB converter while modifying the second voltage signal.

Abstract: A DC/DC converter applies a dual active bridge (DAB) topology to convert an input DC voltage into an output DC voltage. The DC/DC converter includes a transformer, a primary stage, and a secondary stage. The primary stage includes an inductor, a first H-bridge arm having first and second power switches connected at a first node therebetween, and a second H-bridge arm having first and second capacitors connected at a second node therebetween. The inductor is connected between the first node and a terminal of an input port of the primary stage. The primary stage receives the input DC voltage at the input port of the primary stage and converts the input DC voltage into a first AC voltage. The transformer transforms the first AC voltage into a second AC voltage. The secondary stage converts the second AC voltage into the output DC voltage.

Abstract: Systems and methods for balancing phase currents of the phases of a multiphase converter include alternately connecting the phases during respective intervals to an input current and sampling, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases. While the input current samples are unequal, the intervals are adjusted to minimize inequality of the input current samples and thereby balance the phase currents.

Abstract: Systems and methods for balancing phase currents of the phases of a multiphase converter include alternately connecting the phases during respective intervals to an input current and sampling, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases. While the input current samples are unequal, the intervals are adjusted to minimize inequality of the input current samples and thereby balance the phase currents.

Abstract: A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

Abstract: A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

Abstract: A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

Abstract: A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

Abstract: A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.

Abstract: A method of protecting a net of an integrated circuit against injected crosstalk delay includes steps of: method of protecting a net of an integrated circuit against injected crosstalk delay includes steps of: (a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure; (b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net; (c) estimating an injected crosstalk delay of the selected net from a net aggressor; and (d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.

Abstract: A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.

Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.

Abstract: The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit.