Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A semiconductor integrated circuit device comprises at least first and second circuits said first and second circuits being connected to a shared external connection. The device further comprises a voltage clamp that is operable to limit a voltage at the shared external connection. The voltage clamp can be selectively enabled depending upon whether the first or second circuit is being used.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A semiconductor integrated circuit device comprises at least first and second circuits said first and second circuits being connected to a shared external connection. The device further comprises a voltage clamp that is operable to limit a voltage at the shared external connection. The voltage clamp can be selectively enabled depending upon whether the first or second circuit is being used.