Abstract: A method for controlled phase adjustment and coherent modulation in a radio frequency transceiver is provided. The radio frequency transceiver comprises an analogue circuitry for transmitting and receiving radio frequency signals and an all-digital phase locked loop controlled by a Phase Locked Loop, PLL, Control unit (200). The method comprises: receiving a phase shift, and based thereon, deriving a corresponding digital control signal; inputting the digital control signal to the PLL Control unit (200), the control signal defining a temporary iteration pattern of delays to be used by a configurable delay block, DTC (240); locking a radio frequency oscillator signal of a Digital Controlled Oscillator (220) in the phase locked loop to the temporary iteration pattern of delays; adjusting the phase of the frequency signal in digital circuitry, until the signal phase matches the phase shift defined by the digital control signal.

Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.

Abstract: According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A semiconductor integrated circuit device comprises at least first and second circuits said first and second circuits being connected to a shared external connection. The device further comprises a voltage clamp that is operable to limit a voltage at the shared external connection. The voltage clamp can be selectively enabled depending upon whether the first or second circuit is being used.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.

Abstract: A semiconductor integrated circuit device comprises at least first and second circuits said first and second circuits being connected to a shared external connection. The device further comprises a voltage clamp that is operable to limit a voltage at the shared external connection. The voltage clamp can be selectively enabled depending upon whether the first or second circuit is being used.