Abstract: An apparatus that can also be used for generating the average of two integers. The apparatus can be divided into a plurality of sub-adders that operate on sub-words of the input integers in parallel. Hence, the adder can be used for adding or subtracting one set of two integers wherein each integer is of some predetermined length or a plurality of sets of two integers provided the sum of the lengths of the integers is less than or equal to this predetermined length. The apparatus can also generate the sum, or difference, of each of the sub-words divided by two. The parallel operations can be carried out in response to a single instruction. The results of the division by two are rounded in a manner that eliminates biasing of the results.

Abstract: Circuitry combines a first operand A.sub.0, a second operand A.sub.1, and a third operand X in a blend function to produce a result Z. The result Z has a value equal to X*A.sub.0 +(1-X)* A.sub.1. The circuitry includes a plurality of logic gates organized in rows. When performing the blend operation each logic gates selects either a bit of the first operand A.sub.0 or a bit of the second operand A.sub.1. The selection for each logic gate depends upon bits of the third operand X. More specifically, each of the plurality of rows of logic gates selects the first operand A.sub.0 as output when an associated bit of the third operand X is at logic 1, and selects the second operand A.sub.1 as output when the associated bit of the third operand X is at logic 0. In addition to output generated by the plurality of rows of logic gates, a correction term is generated. For the blend operation, the correction term generated is the second operand A.sub.1.

Abstract: A multiplier is modified to perform a population count. A first value is input to the multiplier in place of a first multiplicand. The first value is an operand upon which the population count is to be performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic one. In partial product rows, certain partial products are forced to logic zero. This is done so that only a single column of partial products is used to calculate the population count. The partial products are then summed to produce a result. The present invention also may be adapted for use with Booth-encoded multipliers.

Abstract: A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree addition is performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits are bits of the second value, starting with the low order bit, which are at intervals equal to a bit length of each addend. Each of the first subset of bits is set to logic one. In partial product rows in the multiplier which correspond to the first subset of bits, certain partial products are forced to logic zero. This is done in such a way that all the addends for the tree addition are aligned in columns of the multiplier. The partial products are then summed to produce a result.

Abstract: A computer system facilitates efficient mixing of multiple sub-word items. Mixing circuitry is connected to a plurality of registers and a result register. The mixing circuitry mixes multiple sub-word items packed into the plurality of registers. The multiple sub-word items, when mixed, are placed in the result register. In the preferred embodiment, the mixing circuitry is implemented using a plurality of multiplexors. Control circuitry, connected to the control inputs of the multiplexors, generates control signals which control the mixing of multiple sub-word items by the multiplexors.