Patents by Inventor Ruchi Bora

Ruchi Bora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250192756
    Abstract: A validation circuit is placed in vicinity of a critical path for testing the critical path. The validation circuit receives test data from the control circuit for testing the critical path. The test data is indicative of a delay value that is associated with the critical path. The validation circuit generates multiple setup signals and an enable signal to facilitate the testing of the critical path based on the test data. The validation circuit generates a first test signal based on the enable signal, and a second test signal based on the first test signal and the setup signals. The second test signal is a delayed version of the first test signal. The validation circuit compares the first test signal and the second test signal. A mismatch between the first test signal and the second test signal indicates deviation from the delay value.
    Type: Application
    Filed: January 29, 2024
    Publication date: June 12, 2025
    Inventors: Ashish Goel, Ajay Sharma, Ruchi Bora, Umesh Pratap Singh
  • Patent number: 12164401
    Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: December 10, 2024
    Assignee: NXP B.V.
    Inventors: Umesh Pratap Singh, Ajay Sharma, Ruchi Bora, Ashish Goel
  • Publication number: 20240320112
    Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 26, 2024
    Inventors: Umesh Pratap Singh, Ajay Sharma, Ruchi Bora, Ashish Goel
  • Patent number: 11222707
    Abstract: A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 11, 2022
    Assignee: NXP USA, Inc.
    Inventors: Rohit Kumar Sinha, Tomasz Szuprycinski, Deepak Mahajan, Ruchi Bora