Patents by Inventor Ruchi Shankar
Ruchi Shankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134548Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Inventors: Shobhit SINGHAL, Ruchi SHANKAR, Sverre BRUBAEK, Praveen KUMAR N
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Publication number: 20240071561Abstract: An electronic system includes a repair MMR coupled with a first SRAM module within a plurality of SRAM modules coupled with each other in a daisy-chain configuration on a repair interface, and coupled with a last SRAM module within the plurality of SRAM modules via the repair interface. The electronic system also includes storage memory configured to store repair data for the plurality of SRAM modules and repair instructions, and processing circuitry. The processing circuitry is configured to, during boot up of the electronic system, read repair data for one or more of the plurality of SRAM modules from the storage memory, create serialized repair data for one or more the plurality of SRAM modules based on the repair instructions and the repair data, and to sequentially transmit the serialized repair data to the MMR.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Robin O. Hoel, Praveen Kumar Narayanan, Ruchi Shankar
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Patent number: 11899954Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: GrantFiled: February 2, 2022Date of Patent: February 13, 2024Assignee: Texas Instruments IncorporatedInventors: Shobhit Singhal, Ruchi Shankar, Sverre Brubaek, Praveen Kumar N
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Publication number: 20230244396Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: ApplicationFiled: February 2, 2022Publication date: August 3, 2023Inventors: Shobhit SINGHAL, Ruchi SHANKAR, Sverre BRUBAEK, Praveen KUMAR N
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Publication number: 20230195565Abstract: In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Ruchi Shankar, Tejas Dhanajirao Salunkhe, Trevor Charles Jones
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Publication number: 20230197143Abstract: A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Ruchi Shankar, Shobhit Singhal, Sverre Brubæk, Praveen Kumar Narayanan
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Publication number: 20230076376Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.Type: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Inventors: Robin O. Hoel, Eric Peeters, Prithvi Shankar Yeyyadi Anantha, Aniruddha Periyapatna Nagendra, Shobhit Singhal, Ruchi Shankar, Prachi Mishra
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Publication number: 20230050729Abstract: In described examples, a processor system includes a mailbox, a hardware security functional block (HSFB, also called a trusted agent herein), a processor, and a processor firewall. The HSFB includes a database configured to store at least one software context access rule. The processor executes multiple software contexts. The HSFB approves or denies an access request received from a debugging tool, via the mailbox, in response to the database and a software context identification (ID) included in the access request. The HSFB sends a message to the processor firewall indicating whether the access request is approved. The processor firewall determines whether to pass instructions to the processor for execution with respect to the identified software context in response to the message.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Eric Thierry Jean Peeters, Gary Augustine Cooper, Robin Osa Hoel, Ruchi Shankar, Prachi Mishra
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Publication number: 20210034089Abstract: A system includes a voltage regulator having an output voltage and a power management system, coupled to the voltage regulator. The power management system operable to determine whether the output voltage is within an active range, set the active range to a first range during a first time, or during a first mode, and set the active range to a second range for a second time, or during a second mode.Type: ApplicationFiled: October 6, 2020Publication date: February 4, 2021Inventors: Ruchi Shankar, Somshubhra Paul, Gaurang Helekar
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Patent number: 10795391Abstract: A system includes a voltage regulator having an output voltage; a power management system, coupled to the voltage regulator, operable to continuously monitor the output voltage to determine whether the output voltage is within a range; and the power management system is operable to set the range to a normal range during normal operation, and is operable to increase the range beyond the normal range during a low power mode and during a wake-up period from a low power mode.Type: GrantFiled: September 4, 2015Date of Patent: October 6, 2020Assignee: Texas Instruments IncorporatedInventors: Ruchi Shankar, Somshubhra Paul, Gaurang Helekar
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Publication number: 20200117633Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Bhargavi Nisarga, Ruchi Shankar
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Patent number: 10545908Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.Type: GrantFiled: February 29, 2016Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhargavi Nisarga, Ruchi Shankar
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Publication number: 20170249166Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventors: Bhargavi Nisarga, Ruchi Shankar
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Publication number: 20170068263Abstract: A system includes a voltage regulator having an output voltage; a power management system, coupled to the voltage regulator, operable to continuously monitor the output voltage to determine whether the output voltage is within a range; and the power management system is operable to set the range to a normal range during normal operation, and is operable to increase the range beyond the normal range during a low power mode and during a wake-up period from a low power mode.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Ruchi Shankar, Somshubhra Paul, Gaurang Helekar